Transitions embedded in between consecutive stimulus/response bits toggle scan cells during shift operations. Specifically, serial shift operations during the scan-in of stimulus and the scan-out of response bits can result in a switching activity in the scan chains, which propagate into the combinational logic, dissipating further dynamic power unnecessarily. An end-result, unless treated properly, could be an unexpected behavior of the design, thereby resulting in a yield loss, or reliability problems. Elevated levels of peak power, which can be the maximum instantaneous power throughout the entire test process, can be the cause of the former problem, while a reason for the latter problem can be rather average power that is the total power dissipation averaged over the duration of the test application process. (See, e.g., P. Girard, “Survey of low-power testing of VLSI circuits,” IEEE Design and Test, vol. 19, no. 3, pp. 82-92, 2002). As the test application process can be dominated by shift operations, average power mostly depends on scan power, and thus, the impact of capture power on average power can be negligible. Capture power can be more of a concern when peak power is the targeted issue.
Various scan power reduction methodologies have been proposed. Many of these methodologies are outlined, for example, in P. Girard, “Survey of low-power testing of VLSI circuits,” IEEE Design and Test, vol. 19, no. 3, pp. 82-92, 2002. The utilization of externally controlled gates or modified scan cell designs (see, e.g., S. Gerstend{umlaut over ( )}rfer and H.-J. Wunderlich, “Minimized power consumption for scan-based BIST,” in International Test Conference, 1999, pp. 77-84; R. Sankaralingam and N. A. Touba, “Inserting test points to control peak power during scan testing,” in International Symposium on Defect and Fault-Tolerance in VLSI Systems, 2002, pp. 138-146; S. Bhunia, H. Mahmoodi-Meimand, D. Ghosh, S. Mukhopadhyay, and K. Roy, “Low-power scan design using first-level supply gating,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 3, pp. 384-395, 2005; and M.-H. Chiu and J. C.-M. Li, “Jump scan: A DFT technique for low power testing,” in VLSI Test Symposium, 2005, pp. 277-282) at the expense of functional performance degradation, appropriate primary input assignments during shift cycles (see, e.g., T.-C. Huang and K.-J. Lee, “An input control technique for power reduction in scan circuits during test application,” in Asian Test Symposium, 1999, pp. 315-320; and N. Nicolici, B. M. Al-Hashimi, and A. C. Williams, “Minimisation of power dissipation during test application in full scan sequential circuits using primary input freezing,” in IET Computers and Digital Techniques, 2000, pp. 313-322), test vector ordering and scan-latch clustering/ordering techniques (see, e.g., V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. M. Reddy, “Techniques for minimizing power dissipation in scan and combinational circuits during test application,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, pp. 1325-1333, 1998; and Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and A. Virazel, “Design of routing-constrained low power scan chains,” in Design, Automation and Test in Europe Conference, 2004, pp. 62-67), modification of test cube compaction (see, e.g., R. Sankaralingam and N. A. Touba, “Controlling peak power during scan testing,” in VLSI Test Symposium, 2002, pp. 153-159), test generation and don't care bit specification (see, e.g., R. Sankaralingam, N. A. Touba, and B. Pouya, “Reducing power dissipation during test using scan chain disable,” in VLSI Test Symposium, 2001, pp. 319-324; S. Remersaro, X. Lin, Z. Zhang, S. M. Reddy, I. Pomeranz, and J. Rajski, “Preferred fill: A scalable method to reduce capture power for scan based designs,” in International Test Conference, 2006, pp. 32.2.1-32.2.10; S. Kajihara, K. Ishida, and K. Miyase, “Test vector modification for power reduction during scan testing,” in VLSI Test. Symposium, 2002, pp. 160-165; J. Saxena, K. M. Butler, V. B. Jayaram, S. Kundu, N. V. Arvind, P. Sreeprakash, and M. Hachinger, “A case study of IR-drop in structured at-speed testing,” in International Test Conference, 2003, pp. 1098-1104; A. Chandra and R. Kapur, “Bounded adjacent fill for low capture power scan testing,” in VLSI Test Symposium, 2008, pp. 131-138; X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, “On low-capture-power test generation for scan testing,” in VLSI Test Symposium, 2005, pp. 265-270; X. Wen, Y. Yamashita, S. Morishima, S. Kajihara, L.-T. Wang, K. W. Saluja, and K. Kinoshita, “Low-capture-power test generation for scan-based at-speed testing,” in International Test Conference, 2005, pp. 1019-1028; X. Wen, S. Kajihara, K. Miyase, T. Suzuki, K. W. Saluja, L.-T. Wang, K. S. Abdel-Hafez, and K. Kinoshita, “A new ATPG method for efficient capture power reduction during scan testing,” in VLSI Test Symposium, 2006, pp. 58-65; and H.-T. Lin and J. C.-M. Li, “Simultaneous capture and shift power reduction test pattern generator for scan testing,” IET Computers and Digital Techniques, vol. 2, no. 2, pp. 132-141, 2008), scan chain design (see, e.g., O. Sinanoglu, I. Bayraktaroglu, and A. Orailoglu, “Test power reduction through minimization of scan chain transitions,” in VLSI Test Symposium, 2002, pp. 166-171; O. Sinanoglu, I. Bayraktaroglu, and A. Orailoglu, “Scan power reduction through test data transition frequency analysis,” in International Test Conference, 2002, pp. 844-850; 0. Sinanoglu and A. Orailoglu, “Test power reductions through computationally efficient, decoupled scan chain modifications,” IEEE Transactions on Reliability, vol. 54, no. 2, pp. 215-223, 2005; and O. Sinanoglu and A. Orailoglu, “Modeling scan chain modifications for scan-in test power minimization,” International Test Conference, pp. 602-611, 2003), shift clock spreading (see, e.g., K. Joshi and E. MacDonald, “Reduction of instantaneous power by ripple scan clocking,” in VLSI Test Symposium, 2005, pp. 271-276), test pattern scrubbing (see, e.g., K. M. Butler, J. Saxena, T. Fryars, and G. Hetherington, “Minimizing power consumption in scan testing: Pattern generation and DFT techniques,” in International Test Conference, 2004, pp. 355-364), and scan chain segmentation via clock gating (see, e.g., T. Yoshida and M. Watari, “A new approach for low power scan testing,” in International Test Conference, 2003, pp. 480-487; L. Whetsel, “Adapting scan architectures for low power operation,” in International Test Conference, 2000, pp. 863-872; P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H. J. Wunderlich, “A modified clock scheme for a low power BIST test pattern generator,” in VLSI Test Symposium, 2001, pp. 306-311; Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A gated clock scheme for low power scan testing of logic ICs or embedded cores,” in Asian Test Symposium, 2001, pp. 253-258; P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici, “Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 7, pp. 1142-1153, 2004; K.-J. Lee, T.-C. Haung, and J.-J. Chen, “Peak-power reduction for multiple-scan circuits during test application,” in Asian Test Symposium, 2000, pp. 453-458; P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “Circuit partitioning for low power BIST design with minimized peak power consumption,” in Asian Test Symposium, 1999, pp. 89-94; and S. Almukhaizim and O. Sinanoglu, “Dynamic scan chain partitioning for reducing peak shift power during test,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 2, pp. 298-302, 2009) have been proposed to deliver savings in test power.
A variety of low-power test solutions targeted for compression-based scan architectures have also been proposed recently. For example, x-filling solutions for addressing capture power (see, e.g., J. Li, X. Liu, Y. Zhang, Y. Hu, X. Li, and Q. Xu, “On capture power-aware test data compression for scan-based testing,” in International Conference on Computer-Aided Design, 2008, pp. 67-72; X. Liu and Q. Xu, “A generic framework for scan capture power reduction in test compression environment,” in International Test Conference, 2008, poster 20; and M.-F. Wu, J.-L. Huang, X. Wen, and K. Miyase, “Power supply noise reduction for at-speed scan testing in lineardecompression environment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 28, no. 11, pp. 1767-1776, 2009), or both shift and capture power (see, e.g., X. Liu and Q. Xu, “On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment,” International Test Conference, p. 9.3, 2009), have attained reductions at the expense of an increase in pattern count. A similar end-result has been observed also with Design-for-Testability (DfT) based solutions in the form of filling some of the chains with constant 0's and disabling capture in scan chains (see, e.g., D. Czysz, M. Kassab, X. Lin, G. Mrugalski, J. Rajski, and J. Tyszer, “Low-power scan operation in test compression environment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 28, no. 11, pp. 1742-1755, 2009), or by disabling the clocks of scan chains (see, e.g., C.-W. Tzeng and S.-Y. Huang, “QC-Fill: Quick- and cool xfilling for multicasting-based scan test,” IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 28, no. 11, pp. 1756-1763, 2009; and C. G. Zoellin, and H. J. Wunderlich, “Low-Power Test Planning for Arbitrary At-Speed Delay-Test Clock Schemes,” in VLSI Test Symposium, 2010, pp. 93-98).
In an effort towards identifying a test power reduction solution that retains compression level intact and that does not interfere with the design flow via intrusive techniques such as clock gating, it has been indicated that the content of the scan chains during scan operations can be irrelevant and unimportant, enabling reduction of transitions in the scan chains during shift cycles. As long as the intended stimulus is delivered prior to the capture cycle and responses are compacted the same way, the quality/application of test can remain intact. Recently, a DfT-based approach (see, e.g., A. Chandra, F. Ng, and R. Kapur, “Low power Illinois scan architecture for simultaneous power and test data volume reduction,” in Design, Automation and Test in Europe Conference, 2008, pp. 462-467), for reducing scan-in power in Illinois scan architecture, has been proposed to reduce test power based on this observation. In this approach, which can be referred to as the Deferred-Broadcast (DB), the broadcast stimulus is distributed from one reference chain into the other chains during the final small fragment of the shift process, thus allowing all-but-one chains to receive constant-0's for the majority of shift cycles. As a result, scan-in power can be reduced, while the intended stimulus can be delivered intact; and, this can be achieved without clock gating.
A shortcoming of the DB architecture (see, e.g., A. Chandra, F. Ng, and R. Kapur, “Low power Illinois scan architecture for simultaneous power and test data volume reduction,” in Design, Automation and Test in Europe Conference, 2008, pp. 462-467) can be that it only targets scan-in power reduction and overlooks scan-out power. While each stimulus and response transition can equally contribute to switching activity during test, scan-out power typically dominates test power; stimulus don't care bits (x's) that remain post-compression can be filled properly (e.g., 0-fill or repeat-fill) to leash the scan-in power, while such a direct control over response transitions, with the exception of probabilistic and inexact simulations, does not exist. Thus, although the DB architecture (see, e.g., A. Chandra, F. Ng, and R. Kapur, “Low power Illinois scan architecture for simultaneous power and test data volume reduction,” in Design, Automation and Test in Europe Conference, 2008, pp. 462-467) can attain savings in scan-in power, these savings may correspond to only a small fraction of the overall scan power.
Accordingly, there may be a need to overcome at least some of such exemplary deficiencies.